module idle_select_comp (
	input[16-1:0]  vld_entry,// Clock
	output[4-1:0] idle_select  // Clock Enable
	  // Asynchronous reset active low
	
);
wire [16-1:0] vld=~vld_entry;
wire [8-1:0] data_8;
wire [4-1:0] data_4;
wire [2-1:0] data_2;


assign idle_select[3]=~(| vld[7:0]);
assign data_8=(~idle_select[3])?vld[7:0]:vld[15:8];

assign idle_select[2]=~(| data_8[3:0]);
assign data_4=(~idle_select[2])?data_8[3:0]:data_8[7:4];

assign idle_select[1]=~(| data_4[1:0]);
assign data_2=(~idle_select[1])?data_4[1:0]:data_4[3:2];

assign idle_select[0]=~ data_2[0];







endmodule
